Earticle

초록

영어

This paper presents a concurrent error detection (CED) technique for a bit-slice of a full-adder. The proposed method involves computing the sum and carry bits in two alternative ways so that transient faults will be detected by comparing the results (Sum and Carry out) obtained from the two computing paths. This technique attempts to reduce the amount of extra hardware and circuit cost. In order to avoid the problem of extra delay we will propagate the result when the first computation is finished so that dependent computation can commence execution as soon as possible. To prove the efficiency of the proposed method, the circuit is simulated in standard CMOS 32nm technology and some transient faults are voluntarily injected into the circuit layout. The proposed design provides a 12.12% saving in transistor count compared to a DMR (Dual Modular Redundancy) style design.

목차

Abstract
 I. INTRODUCTION
 II. PREVIOUS WORK
  A. The Sum Function
  B. The Carry Function
  C. The Complete Computation
 IV. SIMULATION RESULTS
 V. EFFICIENCY OF THE PROPOSED TECHNIQUE
  A. Fault Detection
  B. Overhead
 VI. CONCLUSION
 REFERENCES

키워드

저자

• Chiraz Khedhiri [ Electronic & Microelectronic Laboratory, Monastir, Tunisia ]
• Mouna Karmani [ Electronic & Microelectronic Laboratory, Monastir, Tunisia ]
• Belgacem Hamdi [ Electronic & Microelectronic Laboratory, Monastir, Tunisia, ISSAT, Sousse – Tunisia ]
• Ka Lok Man [ Department of Computer Science and Software Engineering, Xi'an Jiaotong-Liverpool University, Suzhou, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  JoC [Journal of Convergence]

• 간기

  계간

• pISSN

  2093-7741

• eISSN

  2093-775X

• 수록기간

  2010~2015

• 십진분류

  KDC 004 DDC 004