Earticle

초록

영어

A promising choice for signal generation in modern communications systems is direct digital frequency synthesis (DDFS) which is capable of well controlled, rapid changes in signal frequency, over a relatively large frequency range. Unfortunately, a conventional DDFS system requires a high frequency read only memory (ROM) which consumes most of the power. This paper describes a novel low complexity DDFS with smaller lookup table size and lesser hardware overhead. It is based on the Taylor series expansion method for sinusoidal and co-sinusoidal functions combined with an approximation algorithm. It has the advantages of high speed, low complexity, low computational delay and high spectral purity. The proposed DDFS has high SFDR (spurious free dynamic range) and the spectral purity can be as good as 135 dBc.

목차

Abstract
 1. Introduction
 2. Proposed DDFS Algorithm
  2.1. Taylor Series Approximation
  2.2. Proposed Architecture
 3. Condition for Coherent Sampling
 4. Results and Discussions
  4.1. DDFS using LUT Based γ Values
  4.2. DDFS using γ Accumulator
  4.3. Practical Implementation of Proposed DDFS
 5. Conclusion
 References

키워드

저자

• K. Hariharan [ Electronics and Communication Engineering Department, Thiagarajar College of Engineering, Madurai – 625015, India ]
• E. Benitta Hubert [ Electronics and Communication Engineering Department, Thiagarajar College of Engineering, Madurai – 625015, India ]
• K. V. O. Divyalakshmi [ Electronics and Communication Engineering Department, Thiagarajar College of Engineering, Madurai – 625015, India ]
• K. Shamalla [ Electronics and Communication Engineering Department, Thiagarajar College of Engineering, Madurai – 625015, India ]
• V. Abhai Kumar [ Electronics and Communication Engineering Department, Thiagarajar College of Engineering, Madurai – 625015, India ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Smart Home

• 간기

  격월간

• pISSN

  1975-4094

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605