Earticle

초록

영어

The rise in complexity of SOC (System-on-Chip) architectures has brought into focus the need for better communication models for SOCs. The traditional bus based approach is reaching its limit with the emergence of high core count SOCs. The theory and practices of wired communication networks is being applied to tackle communication issues in complex SOCs. This is referred to as the Network on Chip (NOC) model. Routers are one of the most important elements of an on chip network. The underlying architecture of a router is based on a crossbar switch as it offers higher throughput and lower latency due to point-to-point architecture. Homogenous sizes of the input module in the router may not be efficient as some cores may be underutilized while some of them may be overloaded. A heterogeneous size of the input module is preferred for the predicted traffic but bursty in nature. We proposed, input module of size 64_packet array for the most busy node in the design while the most underutilized input module can also satisfy the need of the packet array of size 16. For moderate traffic, the input module with 32 packet array can be an efficient solution. The Islip based IQ_VOQ is the most practical combination, popular in the CISCO router [12000 series]. The input module proposed here is based on Virtual output queuing while Islip scheduling algorithm is based on unfolding and folding concept. First, the RTL implementation of input module for 3-proposed design has been carried out and later it realized using a standard-cell-based ASIC flow using 90 nm saed-typ technology library of Synopsis Educational Design Kit.

목차

Abstract
 1. Introduction to IQ_VOQ [input queuing_virtual output queuing]
  1.1 Summary of the Queuing Techniques
  1.2 Overview of iSLIP Scheduling Algorithm
 2. Function of IQ_VOQ based input_module
 3. Input Block to Handle Uniform and Discrete Traffic
 4. Functional Simulation of the Input Module_32_Packet Array
 5. ASIC [FRONT END] Implementation of Input Module
  5.1 Constraints in the Input Block With Packet Array Size 16, 32, 64.
  5.2 The Following Tables Exhibit the Results Obtained After Synthesis
 6. Summary of the Synthesis Results of Input Module
 7. ASIC Implementation of the input_module [16_32_64] with Second Set of Constraints
 8. Four times Faster Scheduler than IQ_VOQ based_Input Block [Error! Bookmark not defined.]
 9. Conclusion
 References

키워드

저자

• Bhavana S. Pote [ Department of Electronics, Ramdeobaba College of Engineering and Management, Nagpur, India ]
• Rehan Maroofi [ Department of Electronics, Ramdeobaba College of Engineering and Management, Nagpur, India ]
• Vilas N. Nitnaware [ Department of Electronics Design Technology, Ramdeobaba College of Engineering and Management Nagpur, India ]

참고문헌

발행기관

간행물

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• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605