Earticle

초록

영어

Floating Point (FP) arithmetic is widely used in large set of scientific and signal processing computation. Adder/subtractor is one of the common arithmetic operation in these computation. The design of FP adder/subtractor is relatively complex than other FP arithmetic operations. This paper has shown an efficient implementation of adder/subtractor module on a reconfigurable plat-form, which is both area as well as performance optimal. The proposed design has optimized the individual complex components of adder module (like dynamic shifter, leading one detector (LOD), priority encoder), to achieve the better overall implementation. Comparison with the best reported work has been shown in the paper, which proves the merits of proposed design.

목차

Abstract
 1: Introduction
 2: Background
 3: Adder/Subtractor Design
  3.1: Dynamic Shifter Design
  3.2: LOD Design
  3.3: Sign and Exponent Computation
  3.4: Normalization and Rounding
  3.5: Exceptional Case Handling
 4: Implementation Details
 5: Result Comparison & Discussion
 6: Conclusion
 References

키워드

저자

• Manish Kumar Jaiswal [ Department of Electronic Engineering, City University of Hong Kong ]
• Ray C.C. Cheung [ Department of Electronic Engineering, City University of Hong Kong ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Hybrid Information Technology

• 간기

  격월간

• pISSN

  1738-9968

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605