Earticle

초록

영어

The delay and dispersion of the packet train have been widely used in most network measurement tools. The timestamp of the packet is critical for the measurement accuracy. However, timestamping performed either in the application or the kernel layer would be easily affected by the source and destination hosts especially in high-speed network. Therefore, to evaluate the impact of the timestamp precision on the measurement, a high accuracy timestamping hardware system (HATS) based on NetFPGA was designed and implemented. With HATS, the deviation of timestamp accuracy among the application, the kernel and the hardware layers was analyzed.

목차

Abstract.
 1 Introduction
 2 Platform Architecture
 3 System Design
  3.1 Reference NIC
  3.2 Time Stamp
  3.3 Synchronization Mechanism
 4 System Implementation
  4.1 Time Stamp Counter
  4.2 Time Stamp
  4.3 RAM
  4.4 Registers
 5 Experiment Design
  5.1 Experimental Environment
  5.2 Traffic Generation
  5.3 Experiment Design
  5.4 Data Collection and Metrics
 6 Evaluation and Analysis
  6.1 Preprocess
  6.2 One-way Analysis of Variance
  6.3 Relative Deviation Analysis
 7 Related Work
 8 Conclusions
 References

키워드

저자

• Zhiqiang Zhou [ Department of EE Tsinghua University, Beijing, China ]
• Lin Cong [ Department of EE Tsinghua University, Beijing, China ]
• Guohan Lu [ Microsoft Research Asia, Beijing, China ]
• Beixing Deng [ Department of EE Tsinghua University, Beijing, China ]
• Xing Li [ Department of EE Tsinghua University, Beijing, China ]

참고문헌

발행기관

간행물

표지보기 관심저널 등록

• 간행물명

  International Journal of Future Generation Communication and Networking

• 간기

  격월간

• pISSN

  2233-7857

• 수록기간

  2008~2016

• 십진분류

  KDC 505 DDC 605