Earticle

초록

영어

This paper proposes a binarized neural network (BNN) processor supporting residual networks. The processor was fabricated in UMC 40-nm CMOS technology. Test results show that performance and energy efficiency are 1036.8 GOPS, and 66.5 GOPS/mW at 200MHz, respectively.

목차

Abstract
I. INTRODUCTION
II. PROPOSED BINARIZED RESNETE DATA FLOW
III. PROPOSED BNN ARCHITECTURE
IV. IMPLEMENTATION AND RESULTS
V. CONCLUSION
ACKNOWLEDGMENT
REFERENCES

저자

• Jeahack Lee [ SoC Platforrm Research Center, Korea Electronics Technology Institute ]
• Hyeonseong Kim [ SoC Platforrm Research Center, Korea Electronics Technology Institute ]
• Junwon Jeong [ Dept. of Electronics Engineering Sookmyung Women’s University ]
• Kyeongmook Oh [ SoC Platforrm Research Center, Korea Electronics Technology Institute ]
• Byung-Soo Kim [ SoC Platforrm Research Center, Korea Electronics Technology Institute ] Corresponding Author

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